ECM534  Advanced Computer Architecture

Instructor: Prof. Taeweon Suh

Fall 2017

Time: W (2)

Classroom: 309 Uncho Useon

Office hour: After class as needed or by appointment at Lyceum 307

Textbook: Digital Design and Computer Architecture by David M. Harris and Sarah L. Harris, Morgan Kaufmann, 2012

Reference: Computer Organization and Design by David Patterson and John Hennessy, 5th edition, Morgan Kaufmann, 2013

Prerequisites: Digital Logic Design (COSE221 or COMP211), C language

Teaching assistants: 김한이 (hanyeemy at korea ac kr)



09/06: DDCA Book Errata in the 1st edition of the textbook

09/06: First class meeting

09/13: Assignment #1 due on 09/20

09/13: Flipped class: reading assignment on 09/20

          Computer Arch.: ~ Lec2 Machine code,   Digital Logic: ~ Lec3 Combinational Logic #2



Useful article: Modern Microprocessors


Final Project Announcements (Tentative)


MIPS design skeleton: Single-Cycle MIPS Design

Tutorial: Synthesis & Simulation (based on Quartus 13.1 and ModelSim 10.1d)


1st milestone (10%): TA check-off by 6pm on 10/25 (Wed)

          - Experiment with DE0 Board

2nd milestone (5%) ) due in class before class on 11/01 (Wed)

          - Schematic drawing

3rd milestone (25%): TA check-off by 6pm on 11/08 (Wed)

          - Instruction addition to single-cycle MIPS

4th milestone (20%):

          - Pipeline with data hazard detection and handling

5th milestone (20%)

          - Pipeline with control hazard detection and handling

Final Project Demo & Interview (20%)

Class Schedule (Tentative) and Slides


Week Topic Slides (Computer Architecture) Slides (Digital Logic Design) Other Announcement
1: 09/01~09/07 Course Introduction

Lec0 Course Intro

2: 09/08~09/14 Basics Lec1 Basics Lec1 Number Systems


3: 09/15~09/21 Instructions Lec2 Machine code Lec2 Logic Gates MIPS R4000 Datasheet
4: 09/22~09/28 Performance Lec3 Performance Lec3 Combinational Logic #1  
5: 09/29~10/05 MIPS Instructions: Data Processing Lec4 Data Processing Insts Lec3 Combinational Logic #2  
6: 10/06~10/12 MIPS Instructions: Memory Access Lec4 Memory Access Insts Lec4 Sequential Logic #1


7: 10/13~10/19 MIPS Instructions: Branch Lec4 Branch Insts Lec4 Sequential Logic #2


8: 10/20~10/26 Miscellaneous Lec4 Miscellaneous Lec4 Sequential Logic #3


9: 10/27~11/02 Midterm   Lec5 Verilog HDL #1

  Midterm Exam

10: 11/03~11/09 MIPS Design (Single-cycle #1) Lec5 Single-Cycle MIPS #1 Lec5 Verilog HDL #2  
11: 11/10~11/16

MIPS Design (Single-cycle #2)

Lec5 Single-Cycle MIPS #2 Lec5 Verilog HDL #3

12: 11/17~11/23 MIPS Design (Pipeline #1) Lec5 Pipelined MIPS #1 Lec6 Adders


13: 11/24~11/30 MIPS Design (Pipeline #2) Lec5 Pipelined MIPS #2 Lec7 Subtractor  
14. 12/01~12/07 Memory Hierarchy - Cache #1 Lec6 Cache #1 Lec8 ALU, Shifter etc  
15. 12/08~12/14 Memory Hierarchy - Cache #2 Lec6 Cache #2    
16. 12/15~12/21



Final Exam




* MIPS Cross Compiler with Eclipse

     (Optional: Build your own MIPS Cross Compiler under Linux)

* SPIM (MIPS Simulator)


Altera DE0 (Development & Education) Board


1. DE0 Board Intro (DE0 Board User Manual)

2. EDA (Electronics Design Automation) tools: Quartus-II v13.1 (including ModelSim Altera Starter Edition 10.1d)

3. FPGA Pin Assignments in DE0 (excel file mapping inputs and outputs of your design to Cyclone-II FPGA)


Note: The USB device driver is located at your Quartus-II installation directory (In Prof Suh' case, the driver's location is at C:\altera\91\quartus\drivers\usb-blaster). It will be asked when connecting DE0 board to your PC.


* Visit the Altera web at for more information

Previous Quizes & Exams

ECM534 Advanced Computer Architecture 


Spring 2016:

Midterm Exam, Midterm Exam Solutions

Final Exam, Final Exam Solutions



Fall 2014:

Final Exam, Final Exam Solution


Fall 2012:

Midterm Exam, Midterm Exam Solution

Final Take-home Exam



Fall 2010:

Midterm Exam, Midterm Exam Solutions

Final Exam, Final Exam Solution



Fall 2008:

Final Exam, Final Exam Solution