COM506 Computer Design

Prof. Taeweon Suh

Fall 2012

Time: Thursday 2 ~ 4 (10:30am ~ 1:30pm)

Classroom: 232 New Building of College of Education

Office hour: After class as needed or by appointment at Lyceum 307

Textbook:

References:

• Digital Design and Computer Architecture by David M. Harris and Sarah L. Harris, Morgan Kaufmann, 2007

• Computer Architecture: A Quantitative Approach by David Patterson and John Hennessy, 4th edition, Morgan Kaufmann, 2009

• Computer Organization and Design by John Hennessy and David Patterson, 4th edition, Morgan Kaufmann, 2007

• Web materials at http://www.adc.co.kr/

Prerequisites:

Computer Architecture, Computer Logic Design, C & C++ Programming, Linux

Announcements

 

09/06: First class meeting

09/06: Assignment #1:

           Read ch1~ch3 of AE32000 ISA Reference Manual and prepare ppt slides for presentation on WW3

10/01: Assignment #2 due on WW7: IF stage schematic drawing

10/18: Assignment #3 due on WW10: ID stage schematic drawing

           - ISIM simulation for validating the behavior of branch predictor wrt 8-entry instruction queue

11/08: Assignment #4 due on WW12: GShare Branch Predictor Design & Debugging

           - GShare and processor examples

             (HAL SPARC64 V (1997), SiByte MIPS (2000), Broadcom BRCM5000 (2010), and Intel Medfield (2012))

           - www.7-cpu.com for branch predictor configurations of ARM Cortex A8 & A9

11/08: Assignment #5 due on WW14: GShare Branch Predictor Performance Evaluation & Porting to FPGA

11/08: WW15 & WW16: Student Presentations on GShare Design & Evaluation

11/12: Dhrystone Simulation with ISIM on Lucida Platform

Class Schedule (Tentative) and Slides

 

Week Topic Slide Reading Assignment Other Announcement
1: 09/03~09/09 Introduction & Technology Trend Intro

 

  
Technology Trend
2: 09/10~09/16 Pipelining Review Pipelining review  

 
3: 09/17~09/23 EISC & Lucida Intro.   AE32000 ISA Reference Manual  
4: 09/24~09/30 Lucida RTL Analysis & Discussion      
5: 10/01~10/07 Lucida RTL Analysis & Discussion   Fetch Stage  
6: 10/08~10/14 Lucida RTL Analysis & Discussion    
7: 10/15~10/21 Lucida RTL Analysis & Discussion   Assignment #2 Due
8: 10/22~10/28 Midterm Week      
9: 10/29~11/04 Lucida RTL Analysis & Discussion Branch Predictors Fetch & Decoding Stages

 
10: 11/05~11/11 Lucida RTL Analysis & Discussion   Assignment #3 Due
11. 11/12~11/18  Branch Predictor Design      
12. 11/19~11/25  Branch Predictor Design No Class due to KIPS conference   Assignment #4 Due
13. 11/26~12/02 Performance evaluation with Dhrystone Simulation & FPGA-based Emulation      
14. 12/03~12/09     Assignment #5 Due
15. 12/10~12/16 Student Presentations      
16. 12/17~12/23     Final Week

Xilinx ISIM

 

1. ISIM User Guide, ISIM In-Depth Tutorial

         

* Visit the Xilinx web at http://www.xilinx.com for more information